Recent trends in neuromorphic engineering
© The Author(s) 2016
Received: 21 April 2016
Accepted: 14 September 2016
Published: 1 December 2016
Neuromorphic Engineering has emerged as an exciting research area, primarily owing to the paradigm shift from conventional computing architectures to data-driven, cognitive computing. There is a diversity of work in the literature pertaining to neuromorphic systems, devices and circuits. This review looks at recent trends in neuromorphic engineering and its sub-domains, with an attempt to identify key research directions that would assume significance in the future. We hope that this review would serve as a handy reference to both beginners and experts, and provide a glimpse into the broad spectrum of applications of neuromorphic hardware and algorithms. Our survey indicates that neuromorphic engineering holds a promising future, particularly with growing data volumes, and the imminent need for intelligent, versatile computing.
Of late, increasing data volumes have posed a challenge to computing systems in terms of their scalability, particularly those that rely on intensive computation. The key challenge has been to handle the data volumes in such systems, owing to their complex, asynchronous and power-drawing nature . Neuromorphic engineering presents itself as a possible, potential and promising solution to problems of this nature [2, 3]. The broad spectrum of algorithms, devices, circuits and systems that are inspired by the working of mammalian neural systems constitutes of neuromorphic engineering.
There have been several recent review articles in the literature on neuromorphic engineering. A review of methods, issues and challenges in neuromorphic engineering was presented by Ahmed et al. , that provides a primer to the domain. It also highlights challenges and open research areas. A comprehensive tutorial by Rajendran et al.  details algorithms, devices and systems, while emerging memory techniques have been discussed in . DeSalvo et al.  present large-scale energy efficient neuromorphic systems based on resistive memory technologies, as well as for low-power embedded devices . Research directions in applications pertaining to vision, auditory and olfactory applications have been discussed by Vanarse et al. .
The rest of the review is organized as follows. Section “Algorithms” discusses recent algorithms developed in the neuromorphic engineering domain. This is followed by a discussion of hardware implementations in Section “Hardware”, which includes neuromorphic devices and circuits. We then discuss recent applications in Section “Recent applications”. Finally, conclusions and future outlook are presented in Section “Conclusions and future outlook”.
Several machine learning algorithms dealing with big data have evolved till date that harness the compute power of server class machines for optimization . Though offline storage space is often abundant, it is the complexity of the approaches employed in such systems, both in storage and time, that has become crucial to their viability. Newer techniques, for example those that use stochastic approximations to learning algorithms allow us to deal with big data. These have allowed us to simulate approaches in tractable time, given the luxury of heavy computational resources. The important challenge that still needs to be addressed is the feasibility in hardware implementation of these algorithms and approaches, that is eventually critical for realizing practical applications, such as on embedded platforms. The storage and computational capacity available on such platforms is limited, hence the algorithms need to have a low computational complexity, that translates to low-power requirements in hardware. This is where research in neuromorphic engineering seeks to provide new directions.
A challenge for the works in this domain has also been the availability of datasets. To this end, Orchard et al.  have worked towards converting conventional static datasets to neuromorphic datasets, that not only maintains their compatibility with existing vision systems for benchmarking performance, but also involves “creation of information” which is required for realizing the true benefit of neuromorphic systems. Tan et al.  have detailed broader perspectives, motivation and guidelines in this direction. The challenge in availability of datasets for closed-loop neuromorphic systems has been addressed by Stewart et al.  in their work on developing benchmarks for such systems using a minimal solution in a physical embodiment. A visual navigation dataset for neuromorphic systems has been developed by Barranco et al. . An effort for benchmarking bio-inspired solutions via neuromorphic architectures on parallel computing platforms has been made by Diamond et al. . Newer research directions in neuromorphic engineering are majorly directed to address these issues, and we review recent trends in neuromorphic engineering for hardware implementations in the following section.
Digital CMOS solutions
A 65 nm CMOS neuromorphic processor has been designed for unsupervised online learning by Seo and Seok  with 1.2 k digital neurons and 4.7 k latch-based synapses. A CMOS motion sensor for biologically motivated expansion/contraction has been developed by Chiang et al.  which has been found to be suitable for applications such as robotic movement. Knag et al.  developed an ASIC with a computer-vision accelerator for a sparse-coding neural net to learn and extract features from images and video.
Several neuromorphic accelerators have also been designed; a comparison of them with machine learning approaches has been presented by Du et al. . Chen et al.  present a low area (3.02m m 2) and power (485m W) neuromorphic accelerator for implementation of deep and convolutional neural networks. Darwin , by Shen et al., is a neuromorphic hardware co-processor for spiking neural networks on 180nm CMOS technology. NS23 by Shahsavari  is a scalable spiking neural network simulator with memristors for computer vision tasks. Conti et. al.  develop a low-power parallel accelerator called the PULP (Parallel processing Ultra-Low Power platform) for kernel based image processing and vision tasks. Mahajan et al.  develop TABLA, a framework to generate accelerators for machine learning algorithms via stochastic approximations for their FPGA realization. A reconfigurable computing accelerator for various neural network topologies has been developed by Liu et al. .
PuDianNao  by Liu et al. is a neuromorphic accelerator which can run seven machine learning algorithms, viz. k-means, k-nearest neighbors, naive bayes, support vector machines, linear regression, classification trees and deep neural networks. Bojnordi et al.  develop a memristive Boltzmann machine for large scale combinatorial optimization and deep learning. They demonstrate their accelerator on the graph partitioning and boolean satisfiability problems, and obtain 57 × higher performance and 25 × lower energy. Neuromorphic accelerators for mobile platforms were presented by Kim et. al.  with speedups ranging from 23–126 % and power reduction of upto 22 % by using inter and intra neuron parallelism.
GPUs and DSPs
The growth in volumes of data has also propelled investigation into neuromorphic architectures for Graphics Processor Units (GPUs). Though tractable processing speedup has been achieved [30, 31], large memory requirements present a challenge . In this context. Garcia et al.  developed a low-memory requiring system using an evolutionary algorithm for configuration selection and validated their system on optical flow benchmarks. Carlson et al.  presented a simulation environment for large-scale spiking neural nets with evolutionary parameter tuning which harnessed the processing power of GPUs. More recently, Cheung et al.  developed “NeuroFlow”, a scalable platform for spiking neural nets on FPGA. Their system could simulate upto 400,000 neurons in real-time with a speedup of 2.83 times than that of GPUs. Liu et al.  present a optical flow sensor inspired by biological approaches which combines a silicon retina vision sensor with a DSP microcontroller.With recent trends in large-scale machine learning moving towards algorithms requiring heavy computational power, one can expect further developments in this direction gaining significance in the future.
Yi et al.  presented a FPGA based encoder and reservoir design for neuromorphic processors. INsight by Chung et. al.  is an energy-efficient architecture for large-scale neural networks, which obtains an accuracy of 97.64 % on a handwritten image recognition dataset. FPGAs have been used for implementation of a convolutional spiking network for classifying musical notes by Escudero  as well as for biomimetic pattern generation . Feedforward neural nets have been presented by Wang et al.  while spiking neural nets on FPGA have been evaluated by Rodrigues et al.  and Wu et al. . Neuron-astrocyte signalling has been implemented by Nazari et al. , image de-warping by Molin et al. , event-driven vision processing by Yousefzadeh et al.  and Bayesian arithmetic stochastic synthesis by Duarte et al. .
Non-CMOS and hybrid solutions
Principles of design for network-based neuromorphic systems have been presented by Partzsch et al. . A reconfigurable memristive dynamical system has been presented by Bavandpour et al. , which can be applied to learning and dynamical systems. Memristive crossbar circuits have also been demonstrated to be suitable for efficient neural network training by Irina et al. , where they show low error rates using batch and stochastic training approaches for a handwritten digit recognition dataset. Neuro-inspired devices have been developed for unsupervised learning by Chabi et al. [51, 52], as well as for an inference engine by Querlioz et al. . A general model for voltage-controlled memristors has been developed by Kvatinsky et al. . Further, Prezioso et al.  present transistor-free metal-oxide memristor crossbars for binary image classification using a single layer perceptron. Memristor-based self healing circuits have been presented by Gu et al. . Sampath et al.  present a CMOS-memristor based FPGA architecture for memory cells.
Deep neural networks have been presented by Bichler et al. , with the specific focus for development of non-volatile memories, while deep spiking nets have been discussed by Neil et al. . Goal-driven deep learning has been explored by Yamins et al. . Fast and energy-efficient neurmorphic computing by Convolutional Neural Networks  and backpropagation  has been presented by Esser et al.
Models for large-scale spiking neural networks have been explored by Krichmar et al. , Wu et. al.  and Wang et al. ; while aspects related to plasticity of such networks in memristive devices has been studied by Saïghi et al. . Garbin et al.  present phase-change memory (PCM) devices as binary probabilistic synapses in a neuromorphic system for visual pattern recognition. Suri et al.  analyze the resistance-drift effect in PCMs, which have also been used to develop a large scale neural network by Burr et al.  and Boybat et al. . Online gradient descent training has been implemented using memristor-based neural networks by Soudry et al. . In the context of network-based algorithms for machine learning, neuromorphic architectures for deep neural networks have been presented by Indiveri. .
Stochastic memristive synapses based on spintronics have been presented by Vincent et al. [73, 74]. Zhang et al.  present a stochastic switching multi-level cell spin transfer torque MRAM. Zhao et al.  develop logic fabrics using spintronics, while energy-efficient architectures have been presented by Locatelli et al. . Spintronics for low-power computing has been discussed in detail in the tutorial by Zhang et al. .
There have also been several hardware implementations based on memristors independently for memories as well as in conjunction with other devices. Challenges in designing neuromorphic analog non-volatile memories have been discussed by Eryilmaz et al. , while Taha et al.  present the design of auto-associative memory using a multi-valued memristive memory cell. Reliability issues faced in using non-volatile memories as hardware synapses have been presented by Shelby et al. , while large crossbar arrays have been demonstrated by Virwani et al. . Analog computing via multi-gate programmable resistive graphene devices has been presented by Calayir et al. , while a chaos-based CMOS analog neuron has been developed by Zhao et al. .
Moon et al.  present a PCMO (P r 0.7 C a 0.3 M n O 3) based resistive switching analog memory device. Mott memories have been discussed by Zhou et al.  The importance of enforcing criticality as a set-point for the purpose of developing adaptive neuromorphic hardware has been discussed by Srinivasa et al. . A neuromorphic crossbar circuit based on analog memristors has been developed by Xu et al. , which demonstrates that recognition rates of upto 82.5 % on an average can be achieved. Ghaderi et al.  investigate cognitive signal processing on programmable analog hardware.
Synaptic devices for visual systems using Resistive RAMs have been presented by Kang et al. , while multistate registers have been developed by Patel et al. . Vertical RRAMs have been explored for cochlea and convolutional neural nets by Piccolboni , while OxRAM synapses for CNNs have been presented by Garbin et al. . ReRAM devices for neuromorphic computing have been explored by Jang et al. , while an artificial synapse using a memristive switch has been modelled by Wang et al. .
Zhang et al.  present an approach for energy-efficient neuromorphic computing for stochastic learning using multiple perpendicular in-plane magnetic tunnel junctions. Binary Conductive-Bridge RAM (CBRAM) synapses for bio-inspired computing has been presented by Suri et al. [97, 98], while Querlioz et al.  discuss stochastic resonance in an analog current-mode circuit.
The realm of applications for neuromorphic engineering continue to grow at an incredible rate. Newer applications keep emerging, and their comprehensive review could well be non-exhaustive. For the sake of brevity, we restrict our review to recently developed applications.
Applications in vision and robot control
There have been several challenges in the computer vision domain which have benefited by the use of biologically inspired computing approaches, and hardware implementation is imminent for their practical application. These involve tasks ranging from relatively simpler image classification to complex tasks such as robot movement planning, object recognition/detection, among others. Most of these involve processing of large datasets, as image or video sequences are fairly large in size, resulting in high area and power consumption.
A system for object detection to enhance the safety of drivers has been described by Han et. al. , and achieves upto 99 % detection rate. An on-chip implementation has been presented by Kim et al. , while a memristive threshold logic circuit for detecting fast moving objects was presented by Maan et al. . Event-based 3D pose estimation using neuromorphic systems has been discussed by Valeiras et al. . Event-based computation of motion flow has been presented in the work by Giulioni , specifically the extraction of optical flow from a visual scene.
Neuromorphic sensors for robotic vision have been benchmarked in terms of power consumption by Censi et al.  against conventional CMOS sensors, while sensors for high speed signal estimation have been developed by Mueller et al. . A visual pattern recognition system has been developed using memristor array and CMOS neuron by Chu et al. , which has been successfully demonstrated for the task of digit recognition. Another such system by Lorenzi et al.  has been developed for recognition of binary images.
Applications in biomedical and biosignal engineering
Applications for biochemical systems for DNA strain displacement have been presented in the work by Chiang et al. . Biological real-time neuromorphic system has been found in . Population coding of neural activity has been done using a Trainable Analogue Block approach by Thakur et al. .
Neuromorphic hardware design has also been inspired by the motivation to model the behavior of the human brain [112–115]. One aspect in doing this involves investigating brain signals that may be acquired by various modalities (invasive or non-invasive) and developing systems to infer how these vary with the presented stimulus, which is analogous to development of brain-computer interfaces. This involves several challenges: the noise and non-stationarity inherent in these data acqusition modalities, the size of the datasets and the restrictions imposed by the acquisition modality. These are often common to all biomedical signals acquired; and multi-modal setups are often beneficial, but more challenging to implement on a common hardware platform. Works in this domain include an event-based neuromorphic Electroencephalogram (EEG) recording system by Corradi et al. . Park et al.  memristive synapse neural network to recognize human thoughts corresponding to imagined speech of three vowels of the English alphabet. Scott et al.  develop a framework for spatio-temporal modelling of brain data called as NeuCube.
Recording of EEG from the ear has been facilitated by the characterization of recordings done using this modality by Mikkelsen et al. . A neuromorphic system mimicking schizophrenia has been developed by Barzegarjalali . The broader context of biosignal processing has been explored by Kudithipudi , where they design and analyze a neuromemristive reservoir computing architecture for this purpose.
Applications in perception engineering
Applications based on integration with sensory modalities of humans have been widely explored. These include applications based on tactile sensor arrays by Lee et al.  and Ros et al. . Corradi et al.  discuss directions for development of a neuromorphic vestibular system, while an autonomous neuromorphic cognition system has been proposed by Chicca et al. . Applications such as texture categorization using neuromorphic inspired touch have been explored by Rongala et al. , while emotion recognition has been presented by Diehl et al. . This area continues to be an exciting yet complex domain to explore, and one can envisage future research directions guided towards these.
A neuromorphic framework for elastic wave dynamics has been presented by Katayama et al. . Nanomorphic memristors have been used in designing neuromorphic fabric by Manem et al.  that can evaluate boolean functions as well as train a perceptron neural net for images.
A system that can classify musical notes has been presented by Cerezuela-Escudero et al.  on FPGA using a convolutional spiking neural network which gave high accuracies even in the presence of noise. A neuromorphic approach to the cocktail party problem implemented on FPGA has been presented by Thakur et al. . Medical assistive applications such as retinal implants and sensory substitution have been explored by Gaspar et al. . A neurmorphic character recognition system has been simulated by Sheri et al.  using PCMO memristors.
High speed serial interfaces have been presented in the work by Jablonski et al.  for bit-serial SATA AER inter-FPGA communication. A neuromorphic system for Electronic Design Automation (EDA) called the AutoNCS has been presented by Wen et al. . A mixed-signal design for a neuromorphic analog-to-digital converter has been presented by Xu et al. .
A VLSI circuit for random sampling has been presented by Chien et al.  for uniform, exponential and bimodal distributions. A neuromorphic microphone has been incubated by Smith . An authentication system accelerated by a neuromorphic hardware has been presented by Suri et al.  using the CM1K chip. It achieves recognition accuracy of 91 % with power requirement ranging from 487-668 μJ for training and testing on a benchmark dataset.
Conclusions and future outlook
Summary of trends in Neuromorphic Engineering
Multi-GPU, Garcia et al. 
3.71 × speedup
Motion Estimation System
Memristive Dynamical System, Bavandpour et al. 
4n memristors and no switch for implementing an n-cell system
Similar to Cellular Memristive Dynamical System (CMDS)
FitzHugh-Nagumo (FHN), Adaptive Exponential (AdEx) integrate and fire, and Izhikevich neuron models
Spiking Deep Neural Nets, Indiveri et al. 
cxQuad (43.79 m m 2), ROLLS (51.4 m m 2)
cxQuad(945uW @1.8 V), ROLLS (4 mW @1. 8V)
Upto 100 % accuracy on toy problems
Event-based convolutional stage for feature extraction connected to a spike-based learning stage for feature classification.
Memristive Boltzmann Machine, Bojnordi et al. 
25 × lower energy compared to multicore system, fully utilized accelerator chip consumes 1.3W
57 × higher performance compared to multicore system
Hardware Accelerator for Combinatorial Optimization and Deep Learning
Processor (PuLP), Conti et al. 
Overall cluster area is 1.2 m m 2.
Peak theoretical energy efficiency of 211 GOPS/W, achieved upto 192 GOPS/W
Scaled over a 1 × to 354 × range,
Parallel Ultra Low-power Processor for ConvNet-based detector for smart surveillance, 4 Open-RISC cores, 64 kB of L2 memory and 24 kB of TCDM fabricated in 28nm STMicroelectronics FD-SOI technology
Processor (Mobile), Kim et al. 
Area overhead of 9 %
energy-savings of 22 %
Average speedups of 126 % and 23 % over CPU and a state-of- the-art MLP accelerator
Neural Network Accelerator for Mobile Application Processors, applied for edge detection
Memristor Based Crossbar, Liu et al. 
0.943 m m 2 (M-net) and 1.793 m m 2 (D-net)
184.2 × (25.23 ×) energy saving over MLP(AAM)
178.4 × (27.06 ×) performance speedup over MLP(AAM)
RENO: Reconfigurable Neuromorphic Computing Accelerator benchmarked with Multi-layer perceptron and Auto-associative memory
Accelerator for machine learning, Liu et al. 
3.51 m m 2
1.20 × faster than NVIDIA K20M GPU
PuDianNao: A Polyvalent Machine Learning Accelerator
Hardware Co-processor, Shen et al. 
5 × 5 m m 2
0.84 mW/MHz with 1.8 V power supply
92.7 % classification accuracy
Darwin Neuromorphic co-processor unit for spiking and artificial neural nets
Accelerator for large scale neural networks, Chung et al. 
3.02 m m 2
117.87 × faster, and it can reduce the total energy by 21.08 ×
For convolutional and deep neural networks
CMOS Motion Sensor, Chiang et al. 
4 × 4 m m 2, 86.2 % fill factor
6.8 % for ± X motion, 3.5 % for ± Y motion, and 6 % for ± Z motion
Motion sensor for Z-motion direction/velocity detection
ASIC Neural Network, Knag et al. 
3.06 mm × 65 nm CMOS ASIC test chip
6.67 mW for a 140 Mpixel/s throughput at 35 MHz.
Memory bit error rate of 0.01
ASIC for image and video feature extraction
Vertical Resistive RAM, Piccolboni et al. 
Area gain of 3-10
98 % recognition rate
For Cochlea and CNN applications
CMOS Analog VLSI Circuit, Chien et al. 
330 μ m × 210 μ m
Theoretically linear relationship between output ISI distribution and input current
Spike-based random sampling
Memristor Array+CMOS Neuron, Chu et al. 
55–100 % recogntion rate based on noise level
Digit recognition task
Neuromorphic Bio-amplifier, Corradi et al. 
0.178 m m 2
90 μ W
96 % classification accuracy
EEG bio-amplifier has a programmable gain of 45–54 dB, with a Root Mean Squared (RMS) input-referred noise level of 2.1 μ V
Arithmetic Units, Kim et al. 
121 μ m 2
0.098 % error rate
Approximate adders and comparators
Processor + on-chip learning, Kim et al. 
1.8 m m 2
classification accuracy to 90 %
256 neurons, 83K synapses for Spiking LCA with classification for object detection
Tactile Sensors for Touch,Lee et al. 
37 × 43.5 c m 2 active sensor area
4096 element tactile sensor array that can be sampled at over 5 kHz
Kilohertz Kilotaxel Tactile Sensor Array for Investigating Spatiotemporal Features
RRAM Multistate Register, Lorenzi et al. 
2.8–5.2 μ m 2
6.5 % energy reduction
40 % improvement over switch-on-event processor
Multistate register for continuous flow multithreading
CM1K chip, Suri et al. 
668 μJ for learning and 487 μJ for recognition, while operating at 25 MHz
91 % recognition accuracy
Multi-modal authentication (person identification) system based on simultaneous recognition of face and speech data
Switched Capacitor Circuit, Mayr et al. 
600 μm × 600 μm
Short and Long term plasticity, 8k synapses
Closed loop interface to in-vitro cortical neuron cultures.
It is clear that advances in technology are allowing for faster devices that are smaller. The diversifying nature of progress in the neuromorphic engineering domain mandates the urgent and strong need of standardization, benchmarking and road-mapping, primarily among various design elements such as neuron blocks, weight blocks, algorithms, communication protocols and test datasets. A look at how integration has progressed in VLSI indicates that power consumption and interconnection complexity have become the most critical hurdles in building larger systems on chip.
We believe that this observation holds pointers for the evolution of neuromorphic systems. In a system with N interacting modules, the data flows and interconnections tend to grow as α N×N, or α N 2. Communication, therefore, consumes more power than the dissipation within individual modules. This is also true for the area of modules on VLSI systems - interconnect occupies more space than logic, and increasingly so. Devices that consume less power are therefore more attractive; technologies that can allow interconnects to scale will tend to dominate. One might expect optical interconnects to become more pervasive. On the algorithms front, sparse representations that lead to reductions in power and area are likely to be more favoured. Coding techniques that make communications more efficient would also be preferred . The last two have a firm mathematical basis, and one might expect to see significant developments along these lines.
The corresponding author would like to acknowledge the support of the Microsoft Chair Professor project grant (MI01158, IIT Delhi). Manan Suri wishes to acknowledge DST project grant RP03051. Sumit Soman would like to acknowledge Aashish Rajiv for his help in collating data for Fig. 1 and preparing Fig. 2.
Sumit Soman is a PhD candidate at the Department of Electrical Engineering, Indian Institute of Technology (llT), Delhi, India. He is also a Technical Officer with the Health Informatics Design and Development group at the Centre for Development of Advanced Computing (CDAC). His research interests include brain computer interfacing and machine learning. Email: firstname.lastname@example.org
Jayadeva is a Professor in the Department of Electrical Engineering at IIT Delhi. He currently holds the Microsoft Chair at IIT Delhi. He is an Associate Editor of the IEEE Transactions on Neural Networks, the IEEE Transactions on Cybernetics, and is an Editor of the IETE Journal of Research. He has served on the Steering and Program Committees of several international conferences. His group was amongst the first to fabricate a SVM based application VLSI ASIC, that contained an A/D converter using a bank of analog SVM classifiers. It also demonstrated a new way of achieving self-calibration in analog circuits. Notable recent work includes the Twin SVM, that is insensitive to class imbalance. It has around 450 citations and is the subject of review articles in AI Review, the Egyptian Informatics Journal, and Neural Computing and Applications (Springer). Work in Ant Colony Optimization includes EigenAnt - the only ACO algorithm with mathematical proofs of convergence and stability from arbitrary initial conditions and for arbitrary parameter choices. An EigenAnt based routing chip has been fabricated in 180 nm CMOS and tested, and is possibly one of the first ACO applications on silicon. Email: email@example.com, Web: http://web.iitd.ac.in/~jayadeva/
Manan Suri received his PhD in Nanoelectronics and Nanotechnology from Institut Polytechnique de Grenoble (INPG), France in 2013. He obtained his M.Eng. (2010) and B.S. (2009) degrees in Electrical and Computer Engineering from Cornell University, USA. Prior to joining IIT Delhi as an Assistant Professor in 2014, he worked as a Senior Scientist with NXP Semiconductors, Central R & D, Leuven, Belgium. His research interests include semiconductor devices, non-volatile memory technology and unconventional ubiquitous computing. He holds several US & European patents. He has authored book chapters and more than 20 papers in reputed international conferences and journals. He serves as committee member and reviewer for IEEE journals/conferences. He has received several prestigious international honors and awards in his field. Email: firstname.lastname@example.org, Web: http://web.iitd.ac.in/~manansuri/.
The authors declare that they have no competing interests.
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